LTC1275ACSW datasheet(16/24 Pages) LINER

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LTC1273

LTC1275/LTC1276

127356fa

APPLICATI

I FOR ATIO

Figure 13. Slow Memory Mode, Parallel Read Timing Diagram

Table 2. Slow Memory Mode, Parallel Read Data Bus Status

Data Outputs

D11

D10

D3/11

D2/10

D1/9

D0/8

Read

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

8MSBs) where it can be read in two read cycles. The

4MSBs always appear on D11...D8 whenever the three-

state output drivers are turned on.

Slow Memory Mode, Parallel Read (HBEN = LOW)

Figure 13 and Table 2 show the timing diagram and data

bus status for Slow Memory Mode, Parallel Read. CS and

RD going low trigger a conversion and the ADC acknowl-

edges by taking BUSY low. Data from the previous conver-

sion appears on the three-state data outputs. BUSY re-

turns high at the end of conversion when the output

latches have been updated and the conversion result is

placed on data outputs D11...D0/8.

Slow Memory Mode, Two Byte Read

For a two byte read, only 8 data outputs D7...D0/8 are used.

Conversion start procedure and data output status for the

first read operation are identical to Slow Memory Mode,

Parallel Read. See Figure 14 timing diagram and Table 3

data bus status. At the end of the conversion, the low data

byte (D7...D0/8) is read from the ADC. A second READ

operation, with the HBEN high, places the high byte on data

outputs D3/11...D0/8 and disables conversion start. Note

on all three inputs to initiate a conversion. Once initiated it

cannot be restarted until the conversion is complete.

Converter status is indicated by the BUSY output, and this

is low while conversion is in progress.

There are two modes of operation as outlined by the timing

diagrams of Figures 13 to 16. Slow Memory Mode is

designed for microprocessors which can be driven into a

WAIT state. A READ operation brings CS and RD low which

initiates a conversion and data is read when conversion is

complete. The second is the ROM Mode which does not

require microprocessor WAIT states. A READ operation

brings CS and RD low which initiates a conversion and

reads the previous conversion result.

Data Format

The output format can be either a complete parallel load for

16-bit microprocessors or a two byte load for 8-bit micro-

processors. Data is always right justified (i.e., LSB is the

most right-hand bit in a 16-bit word). For a two byte read,

only data outputs D7...D0/8 are used. Byte selection is

governed by the HBEN input which controls an internal

digital multiplexer. This multiplexes the 12-bits of conver-

sion data onto the lower D7...D0/8 outputs (4MSBs or

t11

t10

t12

tCONV

OLD DATA

DB11-DB0

NEW DATA

DB11-DB0

TRACK

HOLD

DATA

BUSY

LTC1273/75/76 • F13

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