LTC1867LAIGN datasheet(8/16 Pages) LINER

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LTC1863L/LTC1867L

1863L7Lf

TI I G DIAGRA S

t5 (SDI Setup Time Before SCK↑),

t6 (SDI Hold Time After SCK↑)

50%

0.45V

t7 (SLEEP Mode Wake-Up Time)

SCK

CS/CONV

t8 (BUS Relinquish Time)

CS/CONV

SDO

1.9V

t4 (SDO Valid After CS/CONV↓)

CS/CONV

SDO

1.9V

0.45V

1.9V

0.45V

SCK

SDI

1.9V

0.45V

1.9V

0.45V

SDO

1863L7L TD

SLEEP BIT (SLP = 0)

READ-IN

10%

90%

Hi-Z

t1 (For Short Pulse Mode)

t2 (SDO Valid After SCK↓),

t3 (SDO Valid Hold Time After SCK↓)

CS/CONV

SCK

50%

Overview

The LTC1863L/LTC1867L are complete, low power, multi-

plexed ADCs. They consist of a 12-/16-bit, 175ksps capaci-

tive successive approximation A/D converter, a precision

internal reference, a configurable 8-channel analog input

multiplexer (MUX) and a serial port for data transfer.

Conversions are started by a rising edge on the CS/CONV

input. Once a conversion cycle has begun, it cannot be

restarted. Between conversions, the ADCs receive an input

word for channel selection and output the conversion

result, and the analog input is acquired in preparation for

the next conversion. In the acquire phase, a minimum time

of 2.01µs will provide enough time for the sample-and-

hold capacitors to acquire the analog signal.

During the conversion, the internal differential 16-bit

capacitive DAC output is sequenced by the SAR from the

most significant bit (MSB) to the least significant bit

(LSB). The input is sucessively compared with the binary

weighted charges supplied by the differential capacitive

DAC. Bit decisions are made by a low power, differential

comparator that rejects common mode noise. At the end

of a conversion, the DAC output balances the analog input.

The SAR content (a 12-/16-bit data word) that represents

the analog input is loaded into the 12-/16-bit output

latches.

APPLICATIO S I FOR ATIO

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