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LTC3811

3811f

x-axis. The output ripple current is normalized against

the inductor ripple current at zero duty factor. The graph

can be used in place of tedious calculations. As shown in

Figure 6, the zero output ripple current is obtained

when:

OUT

where k = 1, 2, ..., N – 1

So the number of phases used can be selected to minimize

the output ripple current and therefore the output ripple

voltage at the given input and output voltages. In appli-

cations having a highly varying input voltage, additional

phases will produce the best results.

Accepting larger values of ΔIL allows the use of low in-

ductances, but can result in higher output voltage ripple.

A reasonable starting point for setting ripple current is

ΔIL = 0.4(IOUT)/N, where N is the number of channels and

IOUT is the total load current. Remember, the maximum

ΔIL occurs at the maximum input voltage. The individual

inductor ripple currents are constant determined by the

inductor, input and output voltages.

0.1

0.2

0.3

0.4

0.5

0.6

0.7

30μs

3811 F07

TIME

0.54V = UV

THRESHOLD

0.66V = OV

THRESHOLD

TIME

t < 30μs

130μs

Figure 7. PGOOD Filter Timing Diagram

lockout or overtemperature condition. When the FB pin

voltage is within the ±10% window, the internal PGOOD

MOSFET is turned off and the pin is normally pulled up by

an external resistor. The absolute maximum voltage rating

of the PGOOD pins is 7V.

The PGOOD logic contains separate ﬁlters depending on

whether the controller is entering or exiting a fault condi-

tion. When the FB pin is exiting a fault condition (such as

during normal output voltage start-up, prior to regulation),

the PGOOD pin will remain low for an additional 30μs. This

allows the output voltage to reach steady-state regulation

and prevents the enabling of a heavy load from re-triggering

a UVLO condition. When the FB pin is entering either an

undervoltage, UV, or overvoltage, OV, fault condition, the

PGOOD pin will remain high 130μs after the onset of the

fault. This non-integrating ﬁlter prevents noise or short

duration overload conditions from triggering the PGOOD

outputs and causing a false system reset. Figure 7 illustrates

the timing diagram for a hypothetical undervoltage event

on the FB pin, and the resulting PGOOD waveform.

In multiphase applications, one error ampliﬁer is used to

control all of the phase current comparators. In addition,

since the FB pins for the unused error ampliﬁers are con-

nected to INTVCC (in order to three-state these ampliﬁers),

the PGOOD outputs for these ampliﬁers will be asserted.

In order to prevent falsely reporting a fault condition, the

OPERATION (Refer to the Functional Diagram)

DUTY FACTOR (VOUT/VIN)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

3811 F06

6-PHASE

4-PHASE

3-PHASE

2-PHASE

1-PHASE

Figure 6. Normalized Peak Output Current vs

Duty factor [IRMS ≈ 0.3(ΔIO(P-P))]

Power Good Pins (PGOOD1, PGOOD2)

Each PGOOD pin is connected to the open drain of an

internal N-channel pull-down MOSFET. The MOSEFT turns

on and pulls the PGOOD pin low when the corresponding

FB pin is outside a ±10% window around the 0.6V refer-

ence voltage. The PGOOD pin is also pulled low when the

corresponding RUN pin is low, or during an undervoltage

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