LTC4215CUFD-1-PBF datasheet(21/28 Pages) LINER

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LTC4215-1

42151fa

Figure 12. Control Logic for GPIO2 Pin

4215 TA02

RISING

EDGE

DETECT

RISING

EDGE

DETECT

STATUS BIT C0

ALERT ENABLE BIT B0

POWER ON RESET

I2C ADDRESS ACK

STATUS BIT C5

ALERT ENABLE BIT B5

GPIO2 PIN

APPLICATIONS INFORMATION

Acknowledge

The acknowledge signal is used in handshaking between

transmitter and receiver to indicate that the last byte of

data was received. The transmitter always releases the

SDA line during the acknowledge clock pulse. When the

slave is the receiver, it pulls down the SDA line so that it

remains LOW during this pulse to acknowledge receipt

of the data. If the slave fails to acknowledge by leaving

SDA high, then the master may abort the transmission by

generating a STOP condition. When the master is receiv-

ing data from the slave, the master pulls down the SDA

line during the clock pulse to indicate receipt of the data.

After the last byte has been received the master leaves

the SDA line HIGH (not acknowledge) and issues a stop

condition to terminate the transmission.

Write Protocol

The master begins communication with a START condition

followed by the seven bit slave address and the R/W bit set

to zero, as shown in Figure 7. The addressed LTC4215-1

acknowledges this and then the master sends a command

byte which indicates which internal register the master

wishes to write. The LTC4215-1 acknowledges this and

then latches the lower three bits of the command byte

into its internal Register Address pointer. The master then

delivers the data byte and the LTC4215-1 acknowledges

once more and latches the data into its control register.

The transmission is ended when the master sends a STOP

condition. If the master continues sending a second data

byte, as in a Write Word command, the second data byte

is acknowledged by the LTC4215-1 but ignored, as shown

in Figure 8.

Read Protocol

The master begins a read operation with a START condition

followed by the seven bit slave address and the R/W bit set

to zero, as shown in Figure 9. The addressed LTC4215-1

acknowledges this and then the master sends a command

byte which indicates which internal register the master

wishes to read. The LTC4215-1 acknowledges this and

then latches the lower three bits of the command byte

into its internal Register Address pointer. The master then

sends a repeated START condition followed by the same

seven bit address with the R/W bit now set to one. The

LTC4215-1 acknowledges and send the contents of the

requested register. The transmission is ended when the

LTC4215CUFD-1-PBF Datasheet(PDF) 21 Page - Linear Technology

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