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PCI1221 Datasheet(PDF) 49 Page - Texas Instruments |
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PCI1221 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 123 page  PCI1221 GHK/PDV PC CARD CONTROLLERS SCPS042 – JULY 1998 49 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 latency timer register Bit 7 6 5 4 3 2 1 0 Name Latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Latency timer Type: Read/write Offset: 0Dh Default: 00h Description: The latency timer register specifies the latency timer for the PCI1221 in units of PCI clock cycles. When the PCI1221 is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI1221 transaction has terminated, the PCI1221 terminates the transaction when its GNT is deasserted. This register is separate for each of the two PCI1221 functions. This allows platforms to prioritize the two PCI1221 functions’ use of the PCI bus. header type register Bit 7 6 5 4 3 2 1 0 Name Header type Type R R R R R R R R Default 1 0 0 0 0 0 1 0 Register: Header type Type: Read only Offset: 0Eh (functions 0, 1) Default: 82h Description: This read-only register returns 82h when read, indicating that the PCI1221 functions 0 and 1 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and 80h–FFh is user-definable extension registers. BIST register Bit 7 6 5 4 3 2 1 0 Name BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: BIST Type: Read only Offset: 0Fh (functions 0, 1) Default: 00h Description: Because the PCI1221 does not support a built-in self-test (BIST), this register is read only and returns the value of 00h when read. |
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