01-Jun-2002 Rev. A

Page

3 of 7

ht tp://www.SeCoSGmbH.com/

Any changing of specification will not be informed individual

SSC2156-AD

Part Number

Marking

Output Voltage

Part Number

Marking

Output Voltage

6EAD2

Adjustable

XXXX

Ordering Information(contd.)

Detailed Description

The SSC2156 of COMS regulators contain a PMOS pass transistor,voltage reference, error amplifier,over-current protection and thermal

shutdown.The P-channel pass transistor receives data from the error amplifier, over-current shutdown, and thermal protection circuits.

During normal operation, the error amplifier compares the output voltage to a precision reference. Over-current and Thermal shutdown circuits

become active when the junction temperature exceeds150 C, or the current exceeds 600mA.During thermal shutdown, the output voltage

remains low. Normal operation is restored when the junction temperature drops below 120 C. The SSC2156 switches from voltage mode

o

o

External Capacitors

The SSC2156 is stable with an output capacitance to ground of 2.2uF or greater. Ceramic capacitors have the lowest ESR, and will

offer the best AC performance. Conversely, Aluminum Electrolytic capacitors exhibit the highest ESR, resulting in the poorest AC

response. Unfortunately, large value ceramic capacitors are comparatively expensive. One option is to parallel a 0.1uF ceramic

capacitor with a 10uF Aluminum Electrolytic. The benefit is low ESR, high capacitance, and low overall cost. A second capacitor is

The input capacitor should be at least 0.1uF to have a beneficial

effect. All capacitors should be placed in closed proximity to the pins. A "Quiet" ground termination is desirable. This can be

achieved with a "Star" connection.

Enable

The Enable pin normally floats high. When actively, pulled low, the PMOS pass transistor shuts off, and all internal circuits are powered

down. In this state, the quiescent current is less than 1uA. This pin behaves much like an electronic switch.

ADJ

The ADJ pin is the positive input to the error amplifier which, due to the PMOS pass element inversion, means it is actually the negative

input of the LDO feedback loop. The feedback works to keep the voltage at the ADJ pin 1.215V with respect to ground. Since the internal

circutry at the ADJ pin is essentially an ESD protected CMOS gate the input current at the ADJ pin is virtually zero.

when the load exceeds the rated output current.This prevents over-stress. The SSC2156 also incorporates current fold-back to reduce

power dissipation when the output is short circuited. This feature becomes active when the output drops below 0.8V, and reduces the

current flow by 65%. Full current is restored when the voltage exceeds 0.8V.

Elektronische Bauelemente

SSC2156

600mA CMOS

Positive Voltage Regulator