CLC1606ISO8 datasheet(15/18 Pages) CADEKA

15 / 18 page

Data Sheet

www.cadeka.com

In order to determine PD, the power dissipated in the load

needs to be subtracted from the total power delivered by

the supplies.

PD = Psupply - Pload

Supply power is calculated by the standard power equa-

tion.

Psupply = Vsupply × IRMS supply

Vsupply = VS+ - VS-

Power delivered to a purely resistive load is:

Pload = ((VLOAD)RMS2)/Rloadeff

The effective load resistor (Rloadeff) will need to include

the effect of the feedback network. For instance,

Rloadeff in figure 3 would be calculated as:

RL || (Rf + Rg)

These measurements are basic and are relatively easy to

perform with standard lab equipment. For design purposes

however, prior knowledge of actual signal levels and load

impedance is needed to determine the dissipated power.

Here, PD can be found from

PD = PQuiescent + PDynamic - PLoad

Quiescent power can be derived from the specified IS val-

ues along with known supply voltage, VSupply. Load power

can be calculated as above with the desired signal ampli-

tudes using:

(VLOAD)RMS = VPEAK / √2

( ILOAD)RMS = ( VLOAD)RMS / Rloadeff

The dynamic power is focused primarily within the output

stage driving the load. This value can be calculated as:

PDYNAMIC = (VS+ - VLOAD)RMS × ( ILOAD)RMS

Assuming the load is referenced in the middle of the power

rails or Vsupply/2.

Figure 8 shows the maximum safe power dissipation in the

package vs. the ambient temperature for the 8 and 14 lead

SOIC packages.

0.5

1.5

-40

-20

Ambient Temperature (°C)

SOT23-5

SOIC-8

Figure 8. Maximum Power Derating

Better thermal ratings can be achieved by maximizing PC

board metallization at the package pins. However, be care-

ful of stray capacitance on the input pins.

In addition, increased airflow across the package can also

help to reduce the effective ӨJA of the package.

In the event the outputs are momentarily shorted to a low

impedance path, internal circuitry and output metallization

are set to limit and handle up to 65mA of output current.

However, extended duration under these conditions may

not guarantee that the maximum junction temperature

(+150°C) is not exceeded.

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. CaDeKa has evaluation

boards to use as a guide for high frequency layout and as

aid in device testing and characterization. Follow the steps

below as a basis for high frequency layout:

• Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more in-

formation.

CLC1606ISO8 Datasheet(PDF) 15 Page - Cadeka Microcircuits LLC.

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