SN74ACT3651

2048

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D – JUNE 1994 – REVISED FEBRUARY 1999

12

POST OFFICE BOX 655303

AE Offset

(X)

CLKA

RST

FS1, FS0

4

ENA

IR

A0 – A35

tsu(FS)

th(FS)

tpd(C-IR)

AF Offset

(Y)

First Word Stored in FIFO

th(D)

tsu(D)

tsu(EN)

th(EN)

NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the AF Flag and AE Flag Offset Values From Port A

AE Offset

(X) LSB

CLKA

RST

4

FS1/SEN

IR

FS0/SD

tsu(FS)

th(FS)

tpd(C-IR)

AF Offset

(Y) MSB

th(SD)

tsu(SD)

th(SD)

tsu(SD)

th(SEN)

tsu(SEN)

th(SP)

th(SEN)

tsu(SEN)

tsu(FS)

NOTE A: It is not necessary to program offset-register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set high.

Figure 3. Programming the AF Flag and AE Flag Offset Values Serially