SN74LVC841A

10-BIT BUS-INTERFACE D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCAS307H – MARCH 1993 – REVISED AUGUST 1998

1

POST OFFICE BOX 655303

CMOS) Submicron Process

Live Insertion

All Ports (5-V Input/Output Voltage With

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages

description

The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It

is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and

working registers.

The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true

data at its outputs.

A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC841A is characterized for operation from –40

°C to 85°C.

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

DB, DW, OR PW PACKAGE

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OE

1D

2D

3D

4D

5D

6D

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8D

9D

10D

GND

1Q

2Q

3Q

4Q

5Q

6Q

7Q

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10Q

LE