TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JULY 1998

30

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

scratchpad register

The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended

to be used by the programmer to hold data temporarily.

TXRDY operation

In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO

contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY is asserted (low).

In mode 1, TXRDY is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written

with another byte when TXRDY is asserted (low).

Driver

Optional

Driver

External

Clock

Optional

Clock

Output

Oscillator Clock

to Baud

Generator Logic

VCC

Crystal

Oscillator Clock

to Baud

Generator Logic

RX2

VCC

C1

RP

C2

XTAL1

XTAL1

XTAL2

XTAL2

TYPICAL CRYSTAL OSCILLATOR NETWORK

CRYSTAL

RP

RX2

C1

C2

3.1 MHz

1 M

Ω

1.5 k

Ω

10 – 30 pF

40 – 60 pF

1.8 MHz

1 M

Ω

1.5 k

Ω

10 – 30 pF

40 – 60 pF

Figure 17. Typical Clock Circuits