TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

45

POST OFFICE BOX 1443

buffered serial port transmit timing of external frames

switching characteristics over recommended operating conditions (see Figure 25)

PARAMETER

’549-80

’549-100

’549-120

UNIT

MIN

MAX

td(BDX)

Delay time, BDX valid after BCLKX rising

18

ns

tdis(BDX)

Disable time, BDX after BCLKX rising

4

6

ns

tdis(BDX)pcm

Disable time, PCM mode, BDX after BCLKX rising

6

ns

ten(BDX)pcm

Enable time, PCM mode, BDX after BCLKX rising

8

ns

th(BDX)

Hold time, BDX valid after BCLKX rising

2

ns

timing requirements over recommended operating conditions (see Figure 25)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

tc(SCK)

Cycle time, serial port clock

20

†

ns

tf(SCK)

Fall time, serial port clock

4

ns

tr(SCK)

Rise time, serial port clock

4

ns

tw(SCK)

Pulse duration, serial port clock low/high

6

ns

th(BFSX)

Hold time, BFSX after CLKX falling edge (see Notes 3 and 4)

6

tc(SCK)–6‡

ns

tsu(BFSX)

Setup time, FSX before CLKX falling edge (see Notes 3 and 4)

6

ns

† The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡ If BFSX does not meet this specification, the first bit of the serial data is driven on BDX until BFSX goes low (sampled on falling edge of BCLKX).

After falling edge of the BFSX, data will be shifted out on the BDX pin.

NOTES:

3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined

depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.

4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.