November 2006

ASM5P23S08A

rev 1.5

3.3V ‘SpreadTrak’ Zero Delay Buffer

4 of 17

Notice: The information in this document is subject to change without notice.

Pin Configuration

Pin Description for ASM5P23S08A

Pin #

Pin Name

Description

1

REF

3

Input reference frequency, 5V tolerant input

2

CLKA1

4

Buffered clock output, bank A

3

CLKA2

4

Buffered clock output, bank A

4

3.3V supply

5

GND

Ground

6

CLKB1

4

Buffered clock output, bank B

7

CLKB2

4

Buffered clock output, bank B

8

S2

5

Select input, bit 2

9

S1

5

Select input, bit 1

10

CLKB3

4

Buffered clock output, bank B

11

CLKB4

4

Buffered clock output, bank B

12

GND

Ground

13

3.3V supply

14

CLKA3

4

Buffered clock output, bank A

15

CLKA4

4

Buffered clock output, bank A

16

FBK

PLL feedback input

Notes:

3. Weak pull-down.

4. Weak pull-down on all outputs.

5. Weak pull-up on these inputs.

FBK

CLKA4

GND

CLKB4

CLKB3

S1

S2

CLKB2

CLKB1

GND

REF

ASM5P2308A

CLKA3

CLKA1

CLKA2

9

10

12

13

14

15

16

11

8

7

5

4

3

2

1

6