September 2006

PCS2I9942P

rev 0.4

Low Voltage 1:18 Clock Distribution Chip

2 of 10

Notice: The information in this document is subject to change without notice.

Pin Diagram

Table 2. Pin Description

Pin #

Pin Name

I/O

Type

Function

5

6

PECL_CLK,

PECL_CLK

Input

LVPECL

LVPECL Clock Inputs

3

OE

Input

LVCMOS

Output enable/disable

(high–impedance tristate)

4

NC

No connect

32,31,30,28,27,26,24,23,22,20,19,18,15,

14,13,11,10,9

Q0 – Q17

Output

LVCMOS

Clock outputs

1,2,12,17,25

GND

Supply

Ground

Negative power supply (GND)

for I/O and core.

7,8,16,21,29

Supply

Positive power supply for I/O and

connected to the positive power

supply for correct operation

Table 3. Absolute Maximum Rating

1

Symbol

Parameter

Min

Max

Unit

Supply Voltage

-0.3

3.6

V

Input Voltage

-0.3

V

Input Current

±20

mA

Storage Temperature Range

-40

125

°C

Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect

device reliability.

GND

Q5

Q4

Q3

Q2

Q1

Q0

25

24

26

27

28

29

30

31

32

1

2

3

4

5678

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Q12

Q13

Q14

GND

Q15

Q16

Q17

PCS2I9942P