PCS2I99446 datasheet(6/14 Pages) PULSECORE

6 / 14 page

September 2006

PCS2I99446

rev 0.5

2.5V and 3.3V LVCMOS Clock Distribution Buffer

6 of 14

Notice: The information in this document is subject to change without notice.

Table 9: AC CHARACTERISTICS (V

CC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)

1,2

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

250

MHz

÷1 output

250

MHz

FSELx=0

fMAX

Maximum Output Frequency

÷2 output

125

MHz

FSELx=1

tP, REF

Reference Input Pulse Width

1.4

tr, tf

CCLK Input Rise/Fall Time

1.0

0.7 to 1.7V

CCLK0,1 to any Q

2.6

5.6

tPLH

tPHL

Propagation delay

CCLK0,1 to any Q

2.6

5.5

tPLZ, HZ

Output Disable Time

tPZL, LZ

Output Enable Time

Within one bank

150

Any output Bank,

Same output divider

200

tsk(O)

Output-to-output Skew

Any output, Any output

divider

350

tsk(PP)

Device-to-device Skew

3.0

tSK(P)

Output pulse skew

200

DCQ

Output Duty Cycle

÷1 or ÷2 output

DCREF = 50%

tr, tf

Output Rise/Fall Time

0.1

1.0

0.6 to 1.8V

Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT.

2 AC specifications are design targets, final specification is pending device characterization.

3 The PCS2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.

4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,

output duty cycle and maximum frequency specifications.

5 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.

Table 10: AC CHARACTERISTICS (V

CC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5V + 5% or 3.3V + 5%, TA = –40°C to +85°C)

1,2

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Within one bank

150

Any output Bank, Same output divider

250

tsk(O)

Output-to-output

Skew

Any output, Any output divider

350

tsk(PP)

Device-to-device Skew

2.5

tPLH,HL

Propagation delay

CCLK0,1 to any Q

See 3.3V table

tSK(P)

Output pulse skew

250

DCQ

Output Duty Cycle

÷1 or ÷2 output

DCREF = 50%

Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT.

2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.

3 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.

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