September 2006

PCS2I99447

rev 0.4

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

3 of 14

Notice: The information in this document is subject to change without notice.

Table 1. Function Table

Control

Default

0

1

CLK_SEL

1

CLK0 input selected

CLK1 input selected

OE

1

Outputs disabled (high–impedance state)

1

Outputs enabled

CLK_STOP

1

Outputs synchronously stopped in logic low state

Outputs active

Note: 1. OE = 0 will high–impedance tristate all outputs independent on CLK_STOP

Table 2. Pin Configuration

Pin #

Pin Name

I/O

Type

Function

3

CCLK0

Input

LVCMOS

Clock signal input

4

CCLK1

Input

LVCMOS

Alternative clock signal input

2

CLK_SEL

Input

LVCMOS

Clock input select

5

CLK_STOP

Input

LVCMOS

Clock output enable/disable

6

OE

Input

LVCMOS

Output enable/disable

(high–impedance tristate)

11,13,15,19,21,23,26,28,30

Q0 – Q8

Output

LVCMOS

Clock outputs

1,8,9,12,16,17,20,24,25,29,32

GND

Supply

Ground

Negative power supply (GND) for

Output and Core

7,10,14,18,22,27,31

Supply

Positive power supply for I/O and

to the positive power supply for

correct operation

Table 3. General Specifications

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Output termination voltage

V

MM

ESD protection (Machine model)

200

V

HBM

ESD protection (Human body model)

2000

V

LU

Latch-up immunity

200

mA

Power dissipation capacitance

10

pF

Per output

Input capacitance

4.0

pF

Inputs

Table 4. Absolute Maximum Ratings

1

Symbol

Characteristics

Min

Max

Unit

Condition

Supply Voltage

-0.3

3.9

V

DC Input Voltage

-0.3

V

DC Output Voltage

-0.3

V

DC Input Current

±20

mA

DC Output Current

±50

mA

Storage temperature

-65

125

°C

Note: 1.These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect

device reliability.