TPIC44H01

4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER

SLIS088 – SEPTEMBER 1998

12

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

Table 4. Deglitch Time Encoding

DG1

SDI

BIT5

DG2

SDI

BIT6

DG3

SDI

BIT7

SHORT-TO-GND

DEGLITCH TIME,

t(STG)

(

µs)

SHORT-TO-GND

DUTY CYCLE

WITH:

AR_ENBL=1

OVER-CURRENT

DEGLITCH TIME,

t(OC)

(

µs)

OVER-CURRENT

DUTY CYCLE

WITH:

AR_ENBL=1

AUTO-RETRY

TIME,

t(retry)

(ms)

OPEN-LOAD

DEGLITCH

TIME, t(OL)

(

µs)

0

0

0

16†

0.1%†

120†

0.75%†

16†

120†

0

0

1

4

0.1%

30

0.75%

4

30

0

1

0

8

0.1%

60

0.75%

8

60

0

1

1

32

0.1%

240

0.75%

32

240

1

0

0

120

0.1%

120

0.75%

16

120

1

0

1

30

0.1%

30

0.75%

4

30

1

1

0

60

0.1%

60

0.75%

8

60

1

1

1

240

0.1%

240

0.75%

32

240

† Indicated default conditions after power up.

SDO MSB fault data is setup on the SDO pin by the high-to-low transition of CS prior to the first low-to-high

high-to-low transition to the first rising edge of SCLK to allow the SDO tri-state output to enable and to setup

the fault data MSB on the SDO pin. The remaining 7 bits of fault data are shifted out by the falling edge of the

next 7 SCLK cycles. To prevent data from prematurely shifting out of SDO on a low transition of CS while SCLK

is high, the device requires a low-to-high transition on SCLK after a low transition on CS before the second fault

bit is shifted out. One SCLK cycle is required to clear the serial data register and latch in fault data. If a low

transition on CS occurs without a low-to-high transition on SCLK, then fault data remains in the SDO register

and the device will not latch data into the control register.

The serial register serves as the fault register while CS is high. Thus, a fault occurring any time after the end

of the previous serial interface protocol (low-to-high transition of CS) will be latched as a fault in the serial register

and will be reported via SDO during the next serial protocol. The FLT interrupt will refresh on the high-to-low

transition of CS. The CS input must be driven to a high state after the last bit of serial data has been clocked

into the device. The rising edge of CS will inhibit the SDI input port, put the SDO output port into a high

impedance state, latch the 4 bits of SDI data into the output buffer, and clear/re-enable the serial fault registers

(see Figure 6).

FLT4B

FLT4A

FLT3B

FLT3A

FLT2B

FLT2A

FLT1B

FLT1A

Hi-Z

Hi-Z

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

SCLK

CS

SDO

12

345

6

7

8

Figure 6. SDO Timing Diagram

The TPIC44H01 serial data interface allows multiple devices to be cascaded together to reduce I/O from the

host controller by using a single CS line. In this configuration, 8 bits of data for every cascaded TPIC44H01 must

be sent during the time that CS is low for proper operation (see Figure 7 for an example of two cascaded

TPIC44H01s). If less than 8 bits of data per cascaded device is sent during the time CS is low, the wrong output

may be enabled or disabled, and some fault data will be latched to the output(s) once CS returns high.