LPC2921 datasheet(40/83 Pages) NXP

40 / 83 page

LPC2921_23_25_1

Preliminary data sheet

Rev. 01 — 15 June 2009

40 of 83

NXP Semiconductors

LPC2921/2923/2925

ARM9 microcontroller with CAN, LIN, and USB

6.14.7.1

Pin description

The QEI module in the MSCSS has the following pins. These are combined with other

functions on the port pins of the LPC2921/2923/2925. Table 23 shows the QEI pins.

Remark: The index function for the QEI is not pinned out on the LPC2921/2923/2925.

6.14.7.2

Clock description

The QEI module is clocked by CLK_MSCSS_QEI, see Section 6.7.2. The frequency of

this clock is identical to CLK_MSCSS_APB since they are derived from the same base

clock BASE_MSCSS_CLK.

If the QEI is not used its CLK_MSCSS_QEI branch clock can be switched off.

6.15 Power, clock, and Reset control Sub System (PCRSS)

The Power, Clock, and Reset Control Subsystem (PCRSS) in the LPC2921/2923/2925

includes a Clock Generator Unit (CGU), a Reset Generator Unit (RGU) and a Power

Management Unit (PMU).

Figure 8 provides an overview of the PCRSS. An AHB-to-DTL bridge controls the

communication with the AHB system bus.

Table 23.

QEI pins

Symbol

Pin name

Direction

Description

QEI0 PHA

PHA0

Sensor signal. Corresponds to PHA in

quadrature mode and to direction in

clock/direction mode.

QEI0 PHB

PHB0

Sensor signal. Corresponds to PHB in

quadrature mode and to clock signal in

clock/direction mode.

LPC2921 Datasheet(PDF) 40 Page - NXP Semiconductors