STA2500D datasheet(42/57 Pages) STMICROELECTRONICS

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Digital interfaces

STA2500D

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Doc ID 16067 Rev 1

positive edge of SPI_CLK. When SPI_CSN is inactive, this BT Controller output is in

tristate mode.

●

SPI_DI (on pin BT_UART_RXD/BT_SPI_DI): data transfer from Master to Slave. Data

is generated on the negative edge of SPI_CLK by the Master and sampled on the

positive edge of SPI_CLK.

●

SPI_INT (on pin BT_HOST_WAKEUP/BT_SPI_INT): interrupt from the Slave, used to

request an SPI transfer by the Slave to the Master. The signal is active high (Host input

must be level sensitive).

The SPI interface is Master at the Host side, and Slave at Bluetooth Controller side. It is

designed to work with the H4 and enhanced H4 protocol. Also synchronous data packet

transfer (eSCO) over HCI is supported.

The SPI data length and endianness are configurable.

The SPI interface can only operate in half duplex mode.

Also the use of flow control is configurable. The flow control consists of an indication from

the Bluetooth Controller whether its receive buffers are ready to receive data. This indication

is available in three ways:

●

On the SPI_DO during TSCS (time between SPI_CSN becoming active and SPI_CLK

becoming high), see FC in Figure 17 and Tscs in Figure 18

●

In a register that can be read by the Host

●

Optionally on one of the programmable GPIOs: GPIO_16. This is enabled by a SW

parameter download, see Section 7.5

The default SPI configuration is:

●

Half duplex mode

●

16 bit data length

●

Most significant byte first

●

Most significant bit first

●

Flow control on SPI_DO and in a register

More detailed information on the SPI interface is available upon request.

Figure 17.

SPI data transfer timing for data length of 8 bits and lsb first, full duplex

b1b2b3b4b5b6b7

SPI_CSN

SPI_CLK

SPI_DO

SPI_DI

SPI_INT

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