13 / 19 page
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *J
Page 13 of 19
Notes
43. CE = HIGH for the duration of the above timing (both write and read cycle).
44. IO0R = IO0L = LOW (request semaphore); CER = CEL = HIGH.
45. Semaphores are reset (available to both ports) at cycle start.
46. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Switching Waveforms (continued)
tSOP
tSAA
VALID ADRESS
VALID ADRESS
tHD
DATAIN VALID
DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA
tPWE
tSWRD
tDOE
WRITE CYCLE
READ CYCLE
OE
R/W
IO 0
SEM
A 0–A 2
Figure 10. Semaphore Read After Write Timing, Either Side[43]
MATCH
tSPS
A0L–A2L
MATCH
R/WL
SEML
A 0R–A2R
R/WR
SEM R
Figure 11. Timing Diagram of Semaphore Contention[44, 45, 46]
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