CY2308
Document Number: 38-07146 Rev. *H
Page 7 of 15
t4
Fall Time[7, 8]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30 pF load
–
–
1.25
ns
t5
Output to Output Skew on
same Bank (–1, –2, –3, –4)[7, 8]
All outputs equally loaded
–
–
200
ps
Output to Output Skew
(–1H, –5H)
All outputs equally loaded
–
–
200
ps
Output Bank A to Output Bank
B Skew (–1, –4, –5H)
All outputs equally loaded
–
–
200
ps
Output Bank A to Output Bank
B Skew (–2, –3)
All outputs equally loaded
–
–
400
ps
t6
Delay, REF Rising Edge to
FBK Rising Edge[78]
Measured at VDD/2
–
0
±250
ps
t7
Device to Device Skew[7, 8]
Measured at VDD/2 on the FBK pins of
devices
–0
700
ps
t8
Output Slew Rate[7, 8]
Measured between 0.8V and 2.0V on
–1H, –5H device using Test Circuit 2
1–
–
V/ns
tJ
Cycle to Cycle Jitter[7, 8]
(–1, –1H, –4, –5H)
Measured at 66.67 MHz, loaded
outputs, 15 pF load
–75
200
ps
Measured at 66.67 MHz, loaded
outputs, 30 pF load
––
200
ps
Measured at 133.3 MHz, loaded
outputs, 15 pF load
––
100
ps
tJ
Cycle to Cycle Jitter[7, 8]
(–2, –3)
Measured at 66.67 MHz, loaded
outputs
30 pF load
––
400
ps
Measured at 66.67 MHz, loaded
outputs
15 pF load
––
400
ps
tLOCK
PLL Lock Time[7, 8]
Stable power supply, valid clocks
presented on REF and FBK pins
––
1.0
ms
Switching Characteristics for Industrial Temperature Devices (continued)
Parameter[8]
Name
Test Conditions
Min
Typ
Max
Unit
Switching Waveforms
t1
t2
1.4V
1.4V
1.4V
Figure 3. Duty Cycle Timing
OUTPUT
t3
3.3V
0V
0.8V
2.0V
2.0V
0.8V
t4
Figure 4. All Outputs Rise/Fall Time
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