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LTM9001-Ax/LTM9001-Bx

9001fb

APPLICATIONS INFORMATION

An optional clock duty cycle stabilizer can be used if the

input clock does not have a 50% duty cycle. This circuit

uses the rising edge of ENC to sample the analog input.

The falling edge of ENC is ignored and an internal falling

edge is generated by a phase-locked loop. The input clock

duty cycle can vary from 30% to 70% and the clock duty

cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time,

the duty cycle stabilizer circuit will require one hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin must be

connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the sample rate is determined by the

droop of the sample and hold circuits. The pipelined ar-

chitecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The speciﬁed minimum operating frequency

for the LTM9001 is 1Msps.

DIGITAL OUTPUTS

Digital Output Modes

The LTM9001 can operate in four digital output modes:

standard LVDS, low power LVDS, full rate CMOS, and

demultiplexed CMOS. The LVDS pin selects the mode of

operation. This pin has a four level logic input, centered at

0, 1/3VDD, 2/3VDD and VDD. An external resistive divider

can be used to set the 1/3VDD and 2/3VDD logic levels.

Table 4 shows the logic states for the LVDS pin.

Table 4. LVDS Pin Function

LVDS

DIGITAL OUTPUT MODE

0V(GND)

Full-Rate CMOS

1/3VDD

Demultiplexed CMOS

2/3VDD

Low Power LVDS

VDD

LVDS

Digital Output Buffers (CMOS Modes)

Figure 10 shows an equivalent circuit for a single output

buffer in CMOS mode, full-rate or demultiplexed. Each

buffer is powered by OVDD and OGND, isolated from the

ADC power and ground. The additional N-channel transistor

in the output driver allows operation down to low voltages.

The internal resistor in series with the output makes the

output appear as 50Ω to external circuitry and eliminates

the need for external damping resistors.

9001F8

ENC–

1.6V

VTHRESHOLD = 1.6V

ENC+

0.1μF

LTM9001

Figure 8. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Figure 9. ENC Drive Using a CMOS to PECL Translator

9001 F09

ENC–

ENC+

3.3V

165Ω

261Ω

MC100LVELT22

LTM9001

100Ω

9001 F10

OVDD

VDD

TYPICAL

DATA

OUTPUT

OGND

43Ω

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

LTM9001

Figure 10. Equivalent Circuit for a Digital Output Buffer

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