7

3/5/02

SPT7937

OPERATING DESCRIPTION

The general architecture for the CMOS ADC is shown in

the block diagram. The design contains 18 identical suc-

cessive approximation ADC sections (all operating in par-

allel), an 18-phase clock generator, a 13-bit 18:1 digital

output multiplexer, correction logic, and a voltage refer-

ence generator which provides common reference levels

for each ADC section.

The high sample rate is achieved by using multiple SAR

ADC sections in parallel, each of which samples the input

signal in sequence. Each ADC uses 18 clock cycles to

complete a conversion. The clock cycles are allocated as

follows:

Table II – Clock Cycles

Clock

Operation

1

Reference zero sampling

2

Auto-zero comparison

3

Auto-calibrate comparison

4

Input sample

5-17

13-bit SAR conversion

18

Data transfer

The 18-phase clock, which is derived from the input clock,

synchronizes these events. The timing signals for adjacent

ADC sections are shifted by one clock cycle so that the

analog input is sampled on every cycle of the input clock

by exactly one ADC section. After 18 clock periods, the

timing cycle repeats. The latency from analog input sample

to the corresponding digital output is 14 clock cycles.

• Since only 18 comparators are used, a huge power

savings is realized.

• The auto-zero operation is done using a closed loop

system that uses multiple samples of the comparator’s

response to a reference zero.

• The auto-calibrate operation, which calibrates the gain

of the MSB reference and the LSB reference, is also

done with a closed loop system. Multiple samples of the

gain error are integrated to produce a calibration voltage

for each ADC section.

• Capacitive displacement currents, which can induce

sampling error, are minimized since only one com-

parator samples the input during a clock cycle.

• The total input capacitance is very low since sections of

the converter which are not sampling the signal are

isolated from the input by transmission gates.

VOLTAGE REFERENCE

The SPT7937 requires the use of a single external voltage

reference for driving the high side of the reference ladder. It

must be within the range of 3 V to 5 V. The lower side of the

ladder is typically tied to AGND (0.0 V), but can be run up

to 2.0 V with a second reference. The analog input voltage

full-scale range will track the total voltage difference mea-

Force and sense taps are provided to ensure accurate and

stable setting of the upper and lower ladder sense line volt-

ages across part-to-part and temperature variations. By

using the configuration shown in figure 3, offset and gain

errors of less than ±2 LSB can be obtained.

Figure 3 – Ladder Force/Sense Circuit

AGND

1

2

3

5

6

7

+

–

All capacitors are 0.01 µF

4

N/C