5

5/24/00

SPT7938

Figure 2 – Typical Interface Circuit

FB2

+D3/5V

+

+

EN

CLK

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D0

OTR

1

28

(+4 V)

+A5

FB3

CLK IN

MSB

LSB

+D3/5V

FB1

+

Notes:

1) Unless otherwise specified, all non-polarized capacitors are 0.01 microfarad

surface-mount chip capacitors. They need to be placed as close to the pin as possible.

2) All polarized capacitors are 4.7 to 10 microfarad tantalum surface-mount capacitors.

3) FB1, FB2 and FB3 are ferrite beads. Place FB1 as close to the SPT7938 as possible.

4) U1 is a TOKO regulator, TK112XXB. XX is the regulated output voltage ranging from

1.3 V to 4.8 V with 100 mV increment. For example, TK11240B is a 4.0 V regulator.

Out of Range Bit

AGND

+A5

+

10

+A5

+A5

TK11240B

U1

DGND

+D3/5

+

10

+D3/5

TYPICAL INTERFACE CIRCUIT

stated device performance. Figure 2 shows the typical inter-

face requirements when using the SPT7938 in normal

circuit operation. The following sections provide descrip-

tions of the major functions and outline critical performance

criteria to consider for achieving the optimal device

performance.

POWER SUPPLIES AND GROUNDING

DD

a single analog supply as shown in figure 2. A separate digi-

tal supply should be used for the digital output driver supply

this power supply configuration to prevent a possible latch-

up condition on power up. In addition, the power supplies

must be powered up before the analog input is applied.

Very few external components are required to achieve the

CADEKA suggests that both the digital (DV

) and the ana-

) and all interface circuitry. CADEKA suggests using