Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

25LC640-I/ST Datasheet(PDF) 10 Page - Microchip Technology

Part # 25LC640-I/ST
Description  64K SPI Bus Serial EEPROM
PDF  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

25LC640-I/ST Datasheet(HTML) 10 Page - Microchip Technology

Back Button 25LC640-I/ST Datasheet HTML 6Page - Microchip Technology 25LC640-I/ST Datasheet HTML 7Page - Microchip Technology 25LC640-I/ST Datasheet HTML 8Page - Microchip Technology 25LC640-I/ST Datasheet HTML 9Page - Microchip Technology 25LC640-I/ST Datasheet HTML 10Page - Microchip Technology 25LC640-I/ST Datasheet HTML 11Page - Microchip Technology 25LC640-I/ST Datasheet HTML 12Page - Microchip Technology 25LC640-I/ST Datasheet HTML 13Page - Microchip Technology 25LC640-I/ST Datasheet HTML 14Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 24 page
background image
25AA640/25LC640
DS21223H-page 10
© 2008 Microchip Technology Inc.
3.5
Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX640 is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array and STATUS register, when
set to a ‘0’, the latch prohibits writes to the array and
STATUS register. The state of this bit can always be
updated via the WREN or WRDI commands regardless
of the state of write protection on the STATUS register.
This bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 3-6 for RDSR timing sequence.
FIGURE 3-6:
READ STATUS REGISTER TIMING SEQUENCE
7
654
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
WIP
SO
SI
CS
9
1011
12
1314
15
11
0
0
0
0
00
765
4
2
1
0
Instruction
Data from STATUS Register
High-Impedance
SCK
0
2
3
4567
18
3



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com