P r o d u c t I n n o v a t i o n F r o m

PA73M

PA73MU

1

PA73M/883

SG

PARAMETER

SYMBOL TEMP. POWER

TEST CONDITIONS

MIN

MAX

UNITS

1

Quiescent Current

I

Q

25°C

±28V

V

5

mA

1

Input Offset Voltage

V

OS

25°C

±28V

V

±10

mV

1

Input Offset Voltage

V

OS

25°C

±10V

V

±17.2

mV

1

Input Offset Voltage

V

OS

25°C

±30V

V

±10.8

mV

1

Input Bias Current, +IN

+I

B

25°C

±28V

V

±40

nA

1

Input Bias Current, –IN

–I

B

25°C

±28V

V

±40

nA

1

Input Offset Current

I

OS

25°C

±28V

V

±25

nA

3

Quiescent Current

I

Q

–55°C

±28V

V

5

mA

3

Input Offset Voltage

V

OS

–55°C

±28V

V

±15.2

mV

3

Input Offset Voltage

V

OS

–55°C

±10V

V

±22.4

mV

3

Input Offset Voltage

V

OS

–55°C

±30V

V

±16

mV

3

Input Bias Current, +IN

+I

B

–55°C

±28V

V

±72

nA

3

Input BiasCurrent, –IN

–I

B

–55°C

±28V

V

±72

nA

3

Input Offset Current

I

OS

–55°C

±28V

V

±60

nA

2

Quiescent Current

I

Q

125°C

±28V

V

7

mA

2

Input Offset Voltage

V

OS

125°C

±28V

V

±16.5

mV

2

Input Offset Voltage

V

OS

125°C

±10V

V

±23.7

mV

2

Input Offset Voltage

V

OS

125°C

±30V

V

±17.3

mV

2

Input Bias Current, +IN

+I

B

125°C

±28V

V

±80

nA

2

Input Bias Current, –IN

–I

B

125°C

±28V

V

±80

nA

2

Input Offset Current

I

OS

125°C

±28V

V

±80

nA

4

Output Voltage, I

V

O

25°C

±18.3V

R

10.3

V

4

Output Voltage, I

V

O

25°C

±30V

R

25

V

4

Output Voltage, I

V

O

25°C

±30V

R

24

V

4

Current Limits

I

CL

25°C

±18V

R

.54

.86

A

4

Stability/Noise

E

N

25°C

±28V

R

1

mV

4

Slew Rate

SR

25°C

±28V

R

1

10

V/µs

4

Open Loop Gain

A

OL

25°C

±28V

R

91

dB

4

Common Mode Rejection

CMR

25°C

±15V

R

70

dB

6

Output Voltage, I

V

O

–55°C

±18.3V

R

10.3

V

6

Output Voltage, I

V

O

–55°C

±30V

R

25

V

6

Output Voltage, I

V

O

–55°C

±30V

R

24

V

6

Stability/Noise

E

N

–55°C

±30V

R

1

mV

6

Slew Rate

SR

–55°C

±28V

R

1

10

V/µs

6

Open Loop Gain

A

OL

–55°C

±28V

R

91

dB

6

Common Mode Rejection

CMR

–55°C

±15V

R

70

dB

5

Output Voltage, I

V

O

125°C

±11.3V

R

6.3

V

5

Output Voltage, I

V

O

125°C

±30V

R

25

V

5

Output Voltage, I

V

O

125°C

±30V

R

24

V

5

Stability/Noise

E

N

125°C

±28V

R

1

mV

5

Slew Rate

SR

125°C

±28V

R

1

10

V/µs

5

Open Loop Gain

A

OL

125°C

±28V

R

91

dB

5

Common Mode Rejection

CMR

125°C

±15V

R

70

dB

BURN IN CIRCUIT

*

These components are used to stabilize device

due to poor high frequency characteristics of burn

in board.

**

Input signals are calculated to result in internal

power dissipation of approximately 2.1W at case

temperature = 125°C.

100KΩ

1Ω

1Ω

100KΩ

+15V

–15V

5

6

2

1

8

3

20Ω

**

*

U.U.T

4

*

Table 4 Group A Inspection

PA73M/883

P r o d u c t I n n o v a t i o n F r o m

Copyright © Cirrus Logic, Inc. 2009

(All Rights Reserved)

http://www.cirrus.com

SEP 2009

APEX − PA73MUREVI