MCP3204-BISLASHP datasheet(22/40 Pages) MICROCHIP

22 / 40 page

MCP3204/3208

DS21298E-page 22

FIGURE 6-2:

SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

6.2

Maintaining Minimum Clock Speed

When the MCP3204/3208 initiates the sample period,

charge is stored on the sample capacitor. When the

sample period is complete, the device converts one bit

for each clock that is received. It is important for the

user to note that a slow clock rate will allow charge to

bleed off the sample capacitor while the conversion is

taking place. At 85°C (worst case condition), the part

will maintain proper charge on the sample capacitor for

at least 1.2 ms after the sample period has ended. This

means that the time between the end of the sample

period and the time that all 12 data bits have been

clocked out must not exceed 1.2 ms (effective clock

frequency of 10 kHz). Failure to meet this criterion may

introduce linearity errors into the conversion outside

the rated specifications. It should be noted that during

the entire conversion cycle, the A/D converter does not

require a constant clock speed or duty cycle, as long as

all timing specifications are met.

6.3

Buffering/Filtering the Analog

Inputs

If the signal source for the A/D converter is not a low

impedance source, it will have to be buffered or inaccu-

rate conversion results may occur (see Figure 4-2). It is

also recommended that a filter be used to eliminate any

signals that may be aliased back into the conversion

results, as is illustrated in Figure 6-3, where an op amp

is used to drive the analog input of the MCP3204/3208.

This amplifier provides a low impedance source for the

converter input, and a low pass filter, which eliminates

unwanted high frequency noise.

Low-pass (anti-aliasing) filters can be designed using

Microchip’s free interactive FilterLab® software. Filter-

Lab will calculate capacitor and resistor values, as well

as determine the number of poles that are required for

the application. For more information on filtering

signals, see AN699, “Anti-Aliasing Analog Filters for

Data Acquisition Systems”

10 11 12 13 14 15

SCLK

DIN

X = “Don’t Care” Bits

17 18 19 20 21 22 23 24

DOUT

Don’t Care

NULL

BIT B11 B10 B9

B6 B5 B4 B3 B2 B1 B0

HI-Z

000

XXX

SGL/

DIFF

XXX

B7 B6 B5 B4 B3 B2 B1 B0

B11 B10 B9 B8

????

???

MCU latches data from A/D converter

on rising edges of SCLK

Data is clocked out of A/D

converter on falling edges

SGL/

DIFF

Start

Bit

(Null)

Start

MCU Transmitted Data

(Aligned with falling

edge of clock)

MCU Received Data

(Aligned with rising

edge of clock)

Data stored into MCU receive

8 bits

Data stored into MCU receive

second 8 bits

Data stored into MCU receive

8 bits

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