24LC515 datasheet(7/24 Pages) MICROCHIP

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DS21673G-page 7

24AA515/24LC515/24FC515

5.0

DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a 4-bit control code; for the

24XX515, this is set as ‘1010’ binary for read and write

operations. The next bit of the control byte is the block

select bit (B0). This bit acts as the A15 address bit for

accessing the entire array. The next two bits of the

control byte are the Chip Select bits (A1, A0). The Chip

Select bits allow the use of up to four 24XX515 devices

on the same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

correspond to the logic levels on the corresponding A1

and A0 pins for the device to respond. These bits are in

effect the two Most Significant bits of the word address.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’, a read operation is

selected, and when set to a ‘0’, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). Because

only A14…A0 are used, the upper address bit is a

“don’t care.” The upper address bits are transferred

first, followed by the Less Significant bits.

Following the Start condition, the 24XX515 monitors

the SDA bus checking the device type identifier being

transmitted. Upon receiving a ‘1010’ code and appro-

priate device select bits, the slave device outputs an

Acknowledge signal on the SDA line. Depending on the

state of the R/W bit, the 24XX515 will select a read or

write operation.

This device has an internal addressing boundary

limitation that is divided into two segments of 256K bits.

Block select bit ‘B0’ is used in place of address bit

location ‘A15’ to control access to each segment.

FIGURE 5-1:

CONTROL BYTE

FORMAT

5.1

Contiguous Addressing Across

Multiple Devices

The Chip Select bits A1, A0 can be used to expand the

contiguous address space for up to 2 Mbit by adding up

to four 24XX515’s on the same bus. In this case,

software can use A0 of the control byte as address bit

A16 and A1 as address bit A17. It is not possible to

sequentially read across device boundaries.

Each

device

has

internal

addressing

boundary

limitations. This divides each part into two segments of

256K bits. The block select bit ‘B0’ controls access to

each “half” rather than address bit location A15.

Sequential read operations are limited to 256K blocks.

To read through four devices on the same bus, eight

random Read commands must be given.

FIGURE 5-2:

ADDRESS SEQUENCE BIT ASSIGNMENTS

SACK

R/W

Control Code

Chip

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

Select

Bits

Block

Select

Bit

010

0 R/W

••

•

••

Control Byte

Address High Byte

Address Low Byte

Control

Code

Chip

Select

Bits

X = “don’t care” bit

Block

Select

Bit

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