24LCS22A

DS21682E-page 6

© 2009 Microchip Technology Inc.

FIGURE 3-3:

Communication

is idle

Is Vsync

present?

No

Send EDID™ continuously

using Vsync as clock

High-to-low

transition on

SCL?

No

Yes

Yes

Stop sending EDID.

Switch to DDC2™ mode.

Display has

transition state

?

optional

Set Vsync counter = 0

Change on

VCLK lines?

SCL, SDA or

No

Yes

High-low

transition on SCL

?

Reset Vsync counter = 0

No

Yes

Valid

received?

DDC2 address

No

No

VCLK

cycle?

Yes

Increment VCLK counter

Yes

Switch back to DDC1™

mode.

DDC2 communication

idle. Display waiting for

address byte.

DDC2B

address

received?

Yes

Receive DDC2B

command

Respond to DDC2B

command

Is display

Access.bus™

Yes

Valid Access.bus

address?

No

Yes

See Access.bus

specification to determine

correct procedure.

Yes

No

Yes

No

No

No

The 24LCS22A was designed to

Display Power-on

or

DDC Circuit Powered

from +5 volts

or start timer

Reset counter or timer

(if appropriate)

Counter=128 or

timer expired?

High-to-low

transition on

SCL?

No

Yes

comply to the portion of flowchart inside dash box

Note 1: The base flowchart is copyright

© 1993, 1994, 1995 Video Electronic Standard Association (VESA) from

VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.

2: The dash box and text “The 24LCS22A and... inside dash box.” are added by Microchip Technology Inc.

3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS22A.

capable?