PIC18F44J10 datasheet(125/368 Pages) MICROCHIP

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DS39682E-page 123

PIC18F45J10 FAMILY

12.5

Resetting Timer1 Using the

ECCP/CCP Special Event Trigger

If ECCP1/CCP1 or CCP2 is configured to generate

a Special

Event

Trigger

Compare

mode

(CCPxM<3:0> = 1011), this signal will reset Timer1.

The trigger from CCP2 will also start an A/D conversion

if the A/D module is enabled (see Section 15.2.1

“Special Event Trigger”

for more information).

The module must be configured as either a timer or a

synchronous counter to take advantage of this feature.

When used this way, the CCPRH:CCPRL register pair

effectively becomes a period register for Timer1.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

Special Event Trigger, the write operation will take

precedence.

12.6

Using Timer1 as a Real-Time Clock

Adding an external LP oscillator to Timer1 (such as the

one described in Section 12.3 “Timer1 Oscillator”

above) gives users the option to include RTC function-

ality to their applications. This is accomplished with an

inexpensive watch crystal to provide an accurate time

base and several lines of application code to calculate

the time. When operating in Sleep mode and using a

battery or supercapacitor as a power source, it can

completely eliminate the need for a separate RTC

device and battery backup.

The application code routine, RTCisr, shown in

Example 12-1, demonstrates a simple method to

increment a counter at one-second intervals using an

Interrupt Service Routine. Incrementing the TMR1

the routine which increments the seconds counter by

one. Additional counters for minutes and hours are

incremented as the previous counter overflows.

Since the register pair is 16 bits wide, counting up to

overflow the register directly from a 32.768 kHz clock

would take 2 seconds. To force the overflow at the

required one-second intervals, it is necessary to

preload it. The simplest method is to set the MSb of

TMR1H with a BSF instruction. Note that the TMR1L

introduce cumulative error over many cycles.

For this method to be accurate, Timer1 must operate in

Asynchronous mode and the Timer1 overflow interrupt

must be enabled (PIE1<0> = 1) as shown in the

routine, RTCinit. The Timer1 oscillator must also be

enabled and running at all times.

Note:

The Special Event Triggers from the

ECCP1/CCPx module will not set the

TMR1IF interrupt flag bit (PIR1<0>).

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