PIC18F44J10 datasheet(183/368 Pages) MICROCHIP

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DS39682E-page 181

PIC18F45J10 FAMILY

16.4.9

I2C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit

(SSPxCON2<1>) is programmed high and the I2C logic

module is in the Idle state. When the RSEN bit is set,

the SCLx pin is asserted low. When the SCLx pin is

sampled low, the Baud Rate Generator is loaded with

the contents of SSPxADD<6:0> and begins counting.

The SDAx pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDAx is sampled high, the SCLx

pin will be deasserted (brought high). When SCLx is

sampled high, the Baud Rate Generator is reloaded

with the contents of SSPxADD<6:0> and begins count-

ing. SDAx and SCLx must be sampled high for one

TBRG. This action is then followed by assertion of the

SDAx pin (SDAx = 0) for one TBRG while SCLx is high.

Following this, the RSEN bit (SSPxCON2<1>) will be

automatically cleared and the Baud Rate Generator will

not be reloaded, leaving the SDAx pin held low. As

soon as a Start condition is detected on the SDAx and

SCLx pins, the S bit (SSPxSTAT<3>) will be set. The

SSPxIF bit will not be set until the Baud Rate Generator

has timed out.

Immediately following the SSPxIF bit getting set, the

user may write the SSPxBUF with the 7-bit address in

7-bit mode or the default first address in 10-bit mode.

After the first eight bits are transmitted and an ACK is

received, the user may then transmit an additional eight

bits of address (10-bit mode) or eight bits of data (7-bit

mode).

16.4.9.1

WCOL Status Flag

If the user writes the SSPxBUF when a Repeated Start

sequence is in progress, the WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 16-20:

REPEATED START CONDITION WAVEFORM

Note 1:

If RSEN is programmed while any other

event is in progress, it will not take effect.

A bus collision during the Repeated Start

condition occurs if:

• SDAx is sampled low when SCLx

goes from low-to-high.

• SCLx goes low before SDAx is

asserted low. This may indicate that

another master is attempting to

transmit a data ‘1’.

Note:

Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPxCON2 is disabled until the Repeated

Start condition is complete.

SDAx

SCLx

Sr = Repeated Start

Write to SSPxCON2

Write to SSPxBUF occurs here

on falling edge of ninth clock,

end of Xmit

At completion of Start bit,

hardware clears RSEN bit

1st bit

S bit set by hardware

TBRG

SDAx = 1,

SCLx (no change)

SCLx = 1

occurs here:

TBRG

and sets SSPxIF

RSEN bit set by hardware

TBRG

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