PIC18F44J10 datasheet(196/368 Pages) MICROCHIP

196 / 368 page

PIC18F45J10 FAMILY

DS39682E-page 194

TXSTA: EUSART TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

R-1

R/W-0

CSRC

TX9

TXEN(1)

SYNC

SENDB

BRGH

TRMT

TX9D

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

CSRC:

Clock Source Select bit

Asynchronous mode:

Don’t care.

Synchronous mode:

= Master mode (clock generated internally from BRG)

= Slave mode (clock from external source)

bit 6

TX9:

9-Bit Transmit Enable bit

= Selects 9-bit transmission

= Selects 8-bit transmission

bit 5

TXEN:

Transmit Enable bit(1)

= Transmit enabled

= Transmit disabled

bit 4

SYNC:

EUSART Mode Select bit

= Synchronous mode

= Asynchronous mode

bit 3

SENDB:

Send Break Character bit

Asynchronous mode:

= Send Sync Break on next transmission (cleared by hardware upon completion)

= Sync Break transmission completed

Synchronous mode:

Don’t care.

bit 2

BRGH:

High Baud Rate Select bit

Asynchronous mode:

= High speed

= Low speed

Synchronous mode:

Unused in this mode.

bit 1

TRMT:

Transmit Shift Register Status bit

= TSR empty

= TSR full

bit 0

TX9D:

9th Bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1:

SREN/CREN overrides TXEN in Sync mode.

PIC18F44J10 Datasheet(PDF) 196 Page - Microchip Technology

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