PIC18F44J10-ISLASHSOSQTP datasheet(279/368 Pages) MICROCHIP

279 / 368 page

DS39682E-page 277

PIC18F45J10 FAMILY

NEGF

Negate f

Syntax:

NEGF

f {,a}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

( f ) + 1

→ f

Status Affected:

N, OV, C, DC, Z

Encoding:

0110

110a

ffff

Description:

Location ‘f’ is negated using two’s

complement. The result is placed in the

data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode”

for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example:

NEGF

REG, 1

Before Instruction

REG

0011 1010

[3Ah]

After Instruction

REG

1100 0110

[C6h]

NOP

No Operation

Syntax:

NOP

Operands:

None

Operation:

No operation

Status Affected:

None

Encoding:

0000

1111

0000

xxxx

0000

xxxx

0000

xxxx

Description:

No operation.

Words:

Cycles:

Q Cycle Activity:

Decode

operation

Example:

None.

PIC18F44J10-I/SOSQTP Datasheet(PDF) 279 Page - Microchip Technology

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