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PIC18F44J10-I/SOSQTP Datasheet(PDF) 362 Page - Microchip Technology |
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PIC18F44J10-I/SOSQTP Datasheet(HTML) 362 Page - Microchip Technology |
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362 / 368 page  PIC18F45J10 FAMILY DS39682E-page 360 © 2009 Microchip Technology Inc. Timer0 .............................................................................. 115 Associated Registers ............................................... 117 Clock Source Select (T0CS Bit) ............................... 116 Operation ................................................................. 116 Overflow Interrupt .................................................... 117 Prescaler .................................................................. 117 Prescaler Assignment (PSA Bit) .............................. 117 Prescaler Select (T0PS2:T0PS0 Bits) ..................... 117 Prescaler. See Prescaler, Timer0. Reads and Writes in 16-Bit Mode ............................ 116 Source Edge Select (T0SE Bit) ................................ 116 Switching Prescaler Assignment .............................. 117 Timer1 .............................................................................. 119 16-Bit Read/Write Mode ........................................... 121 Associated Registers ............................................... 124 Interrupt .................................................................... 122 Operation ................................................................. 120 Oscillator .......................................................... 119, 121 Layout Considerations ..................................... 122 Oscillator, as Secondary Clock .................................. 30 Overflow Interrupt .................................................... 119 Resetting, Using the ECCP/CCP Special Event Trigger ....................................... 123 Special Event Trigger (ECCP) ................................. 136 TMR1H Register ...................................................... 119 TMR1L Register ....................................................... 119 Use as a Clock Source ............................................ 122 Use as a Real-Time Clock ....................................... 123 Timer2 .............................................................................. 125 Associated Registers ............................................... 126 Interrupt .................................................................... 126 Operation ................................................................. 125 Output ...................................................................... 126 PR2 Register .................................................... 132, 137 TMR2-to-PR2 Match Interrupt .......................... 132, 137 Timing Diagrams A/D Conversion ........................................................ 334 Acknowledge Sequence .......................................... 185 Asynchronous Reception ......................................... 206 Asynchronous Transmission .................................... 204 Asynchronous Transmission (Back to Back) ........... 204 Automatic Baud Rate Calculation ............................ 202 Auto-Wake-up Bit (WUE) During Normal Operation ............................................. 207 Auto-Wake-up Bit (WUE) During Sleep ................... 207 Baud Rate Generator with Clock Arbitration ............ 179 BRG Overflow Sequence ......................................... 202 BRG Reset Due to SDAx Arbitration During Start Condition ................................................. 189 Brown-out Reset (BOR) ........................................... 322 Bus Collision During a Repeated Start Condition (Case 1) .................................. 190 Bus Collision During a Repeated Start Condition (Case 2) .................................. 190 Bus Collision During a Start Condition (SCLx = 0) ............................... 189 Bus Collision During a Stop Condition (Case 1) ................................... 191 Bus Collision During a Stop Condition (Case 2) ................................... 191 Bus Collision During Start Condition (SDAx Only) ............................ 188 Bus Collision for Transmit and Acknowledge ........... 187 Capture/Compare/PWM (Including ECCP Module) ................................ 324 CLKO and I/O .......................................................... 321 Clock Synchronization ............................................. 172 Clock/Instruction Cycle .............................................. 56 EUSART Synchronous Receive (Master/Slave) ...... 333 EUSART Synchronous Transmission (Master/Slave) ................................................. 333 Example SPI Master Mode (CKE = 0) ..................... 325 Example SPI Master Mode (CKE = 1) ..................... 326 Example SPI Slave Mode (CKE = 0) ....................... 327 Example SPI Slave Mode (CKE = 1) ....................... 328 External Clock (All Modes Except PLL) ................... 319 Fail-Safe Clock Monitor ........................................... 246 First Start Bit Timing ................................................ 180 Full-Bridge PWM Output .......................................... 141 Half-Bridge PWM Output ......................................... 140 I2C Bus Data ............................................................ 329 I2C Bus Start/Stop Bits ............................................ 329 I2C Master Mode (7 or 10-Bit Transmission) ........... 183 I2C Master Mode (7-Bit Reception) .......................... 184 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 169 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 174 I2C Slave Mode (10-Bit Transmission) .................... 170 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 167 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 173 I2C Slave Mode (7-Bit Transmission) ...................... 168 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............ 175 I2C Stop Condition Receive or Transmit Mode ........ 186 Master SSP I2C Bus Data ........................................ 331 Master SSP I2C Bus Start/Stop Bits ........................ 331 Parallel Slave Port (PSP) Read ............................... 114 Parallel Slave Port (PSP) Write ............................... 114 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 146 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 146 PWM Direction Change ........................................... 143 PWM Direction Change at Near 100% Duty Cycle ............................................. 143 PWM Output ............................................................ 132 Repeated Start Condition ........................................ 181 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ..... 322 Send Break Character Sequence ............................ 208 Slave Synchronization ............................................. 155 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 45 SPI Mode (Master Mode) ......................................... 154 SPI Mode (Slave Mode, CKE = 0) ........................... 156 SPI Mode (Slave Mode, CKE = 1) ........................... 156 Synchronous Reception (Master Mode, SREN) ..................................... 211 Synchronous Transmission ..................................... 209 Synchronous Transmission (Through TXEN) .......... 210 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ...................... 45 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ...................... 45 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise /Tpwrt) ............... 44 Timer0 and Timer1 External Clock .......................... 323 Transition for Entry to Idle Mode ................................ 39 Transition for Entry to SEC_RUN Mode .................... 36 Transition for Entry to Sleep Mode ............................ 38 Transition for Two-Speed Start-up (INTRC) ............ 244 |
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