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PIC18F44J10-I/SOSQTP Datasheet(PDF) 363 Page - Microchip Technology |
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PIC18F44J10-I/SOSQTP Datasheet(HTML) 363 Page - Microchip Technology |
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363 / 368 page ![]() © 2009 Microchip Technology Inc. DS39682E-page 361 PIC18F45J10 FAMILY Transition for Wake From Idle to Run Mode .............. 39 Transition for Wake From Sleep ................................ 38 Transition From RC_RUN Mode to PRI_RUN Mode ................................................. 37 Transition to RC_RUN Mode ..................................... 37 Timing Diagrams and Specifications A/D Conversion Requirements ................................ 335 AC Characteristics Internal RC Accuracy ....................................... 320 Capture/Compare/PWM Requirements (Including ECCP Module) ................................ 324 CLKO and I/O Requirements ................................... 321 EUSART Synchronous Receive Requirements .................................................. 333 EUSART Synchronous Transmission Requirements .................................................. 333 Example SPI Mode Requirements (CKE = 0) ................................................. 325, 327 Example SPI Mode Requirements (CKE = 1) ......................................................... 326 Example SPI Slave Mode Requirements (CKE = 1) 328 External Clock Requirements .................................. 319 I2C Bus Data Requirements (Slave Mode) .............. 330 I2C Bus Start/Stop Bits Requirements (Slave Mode) ................................................... 329 Master SSP I2C Bus Data Requirements ................ 332 Master SSP I2C Bus Start/Stop Bits Requirements .................................................. 331 Parallel Slave Port Requirements ............................ 324 PLL Clock ................................................................. 320 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ........................................ 322 Timer0 and Timer1 External Clock Requirements .................................................. 323 Top-of-Stack Access .......................................................... 53 TRISE Register PSPMODE Bit .......................................................... 107 TSTFSZ ........................................................................... 289 Two-Speed Start-up ................................................. 235, 244 Two-Word Instructions Example Cases .......................................................... 57 TXSTA Register BRGH Bit ................................................................. 197 V Voltage Reference Specifications .................................... 316 Voltage Regulator (On-Chip) ........................................... 243 W Watchdog Timer (WDT) ........................................... 235, 242 Associated Registers ............................................... 242 Control Register ....................................................... 242 During Oscillator Failure .......................................... 245 Programming Considerations .................................. 242 WCOL ...................................................... 180, 181, 182, 185 WCOL Status Flag ................................... 180, 181, 182, 185 WWW Address ................................................................ 363 WWW, On-Line Support ...................................................... 6 X XORLW ........................................................................... 289 XORWF ........................................................................... 290 |
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