ACT8712QLCHA-T datasheet(5/36 Pages) ACTIVE-SEMI

5 / 36 page

Rev0, 25-Feb-08

ACT8712

Innovative Products. Active Solutions.

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ActivePMU

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2CTM is a trademark of Philips Electronics.

PIN DESCRIPTIONS

NAME

DESCRIPTION

VIN

Power Input for the Battery Charger. Bypass VIN to GA with a capacitor placed as close to

the IC as possible. The battery charger and both step-down DC/DCs (REG1 and REG2)

are automatically enabled when a valid voltage is present on VIN.

SCL

Clock Input for I2C Serial Interface. Data is read on the rising edge of the clock.

SDA

Data Input for I2C Serial Interface. Data is read on the rising edge of the clock.

nIRQ

Open-Drain Push-Button Status Output. nIRQ is an open-drain output which sinks current

when nMSTR is asserted.

nMSTR

Master Enable Input. Drive nMSTR to GA or to a logic low to enable IC.

nRSTO

Open-Drain Reset Output. nRSTO asserts low for the reset timeout period of 300ms when-

ever the IC is enabled.

OUT1

Output Feedback Sense for REG1. Connect this pin directly to the output node to connect

the internal feedback network to the output voltage.

VP1

Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as

close as possible to the IC.

SW1

Switching Node Output for REG1. Connect this pin to the switching end of the inductor.

GP12

Power Ground for REG1 and REG2. Connect GA, GP12, and GP3 together at a single

point as close to the IC as possible.

SW2

Switching Node Output for REG2. Connect this pin to the switching end of the inductor.

VP2

Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as

close as possible to the IC.

OUT2

Output Feedback Sense for REG2. Connect this pin directly to the output node to connect

the internal feedback network to the output voltage.

ON2

Enable Control Input for REG3. ON2 is functional only when ON1 is driven high, nMSTR is

driven low, or when a valid supply voltage is present on VIN. Drive ON2 to VSYS or to a

logic high for normal operation, drive to GA or a logic low to disable REG3.

ON1

Enable Control Input for REG1 and REG2. Drive ON1 to VSYS or to a logic high for normal

operation, drive to GA or to a logic low to disable REG1 and REG2.

VSYS

Power Bypass for System Management Circuitry. Bypass to GA with a high quality ceramic

capacitor placed as close as possible to the IC. VSYS is internally connected to the higher

voltage of either VVIN or VBAT. Do not load VSYS with more than 100µA.

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