PIC18F2221 datasheet(35/402 Pages) MICROCHIP

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DS39689F-page 35

PIC18F2221/2321/4221/4321 FAMILY

3.7

Clock Sources and Oscillator

Switching

The PIC18F2221/2321/4221/4321 family of devices

includes a feature that allows the device clock source

to be switched from the main oscillator to an alternate

clock source. These devices also offer two alternate

clock sources. When an alternate clock source is

enabled, the various power-managed operating modes

are available.

Essentially, there are three clock sources for these

devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the External Crystal

and Resonator modes, the External RC modes, the

External Clock modes and the internal oscillator block.

The particular mode is defined by the FOSC<3:0> Con-

figuration bits. The details of these modes are covered

earlier in this chapter.

The secondary oscillators are those external sources

not connected to the OSC1 or OSC2 pins. These

sources may continue to operate even after the

controller is placed in a power-managed mode.

The PIC18F2221/2321/4221/4321 family of devices

offers the Timer1 oscillator as a secondary oscillator.

This oscillator, in all power-managed modes, is often

the time base for functions such as a Real-Time Clock.

Most often, a 32.768 kHz watch crystal is connected

between the RC0/T1OSO/T13CKI and RC1/T1OSI

pins. Like the LP mode oscillator circuit, loading

capacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in

Section 13.3 “Timer1 Oscillator”.

In addition to being a primary clock source, the internal

oscillator block is available as a power-managed

mode clock source. The INTRC source is also used as

the clock source for several special features, such as

the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2221/2321/4221/4321

family of devices are shown in Figure 3-11. See

Section 24.0 “Special Features of the CPU” for

Configuration register details.

FIGURE 3-11:

PIC18F2221/2321/4221/4321 FAMILY CLOCK DIAGRAM

4 x PLL

FOSC<3:0>

Secondary Oscillator

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for Other Modules

OSC1

OSC2

Sleep

HSPLL, INTOSC/PLL

LP, XT, HS, RC, EC

T1OSC

CPU

Peripherals

IDLEN

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

OSCCON<6:4>

111

110

101

100

011

010

001

000

31 kHz

INTRC

Source

Internal

Oscillator

Block

WDT, PWRT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

OSCCON<6:4>

Clock

Control

OSCCON<1:0>

Source

8 MHz

31 kHz (INTRC)

OSCTUNE<6>

OSCTUNE<7>

and Two-Speed Start-up

Primary Oscillator

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