PIC18F2221 datasheet(197/402 Pages) MICROCHIP

197 / 402 page

DS39689F-page 197

PIC18F2221/2321/4221/4321 FAMILY

18.4.7

BAUD RATE

In I2C Master mode, the Baud Rate Generator (BRG)

reload value is placed in the lower 7 bits of the

SSPADD register (Figure 18-19). When a write occurs

to SSPBUF, the Baud Rate Generator will automatically

begin counting. The BRG counts down to 0 and stops

until another reload has taken place. The BRG count is

decremented twice per instruction cycle (TCY) on the

Q2 and Q4 clocks. In I2C Master mode, the BRG is

reloaded automatically.

Once the given operation is complete (i.e., transmis-

sion of the last data bit is followed by ACK), the internal

clock will automatically stop counting and the SCL pin

will remain in its last state.

Table 18-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

FIGURE 18-19:

BAUD RATE GENERATOR BLOCK DIAGRAM

TABLE 18-3:

I2C™ CLOCK RATE W/BRG

Fosc

FCY

FCY * 2

BRG Value

FSCL

(2 Rollovers of BRG)

40 MHz

10 MHz

20 MHz

18h

400 kHz

40 MHz

10 MHz

20 MHz

1Fh

312.5 kHz

40 MHz

10 MHz

20 MHz

63h

100 kHz

16 MHz

4 MHz

8 MHz

09h

400 kHz

16 MHz

4 MHz

8 MHz

0Ch

308 kHz

16 MHz

4 MHz

8 MHz

27h

100 kHz

4 MHz

1 MHz

2 MHz

02h

333 kHz

4 MHz

1 MHz

2 MHz

09h

100 kHz

4 MHz

1 MHz

2 MHz

00h

1 MHz

SSPM<3:0>

BRG Down Counter

CLKO

FOSC/4

SSPADD<6:0>

SSPM<3:0>

SCL

Reload

Control

Reload

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