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DLPD3V3LC Datasheet(PDF) 1 Page - Diodes Incorporated |
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DLPD3V3LC Datasheet(HTML) 1 Page - Diodes Incorporated |
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1 / 4 page  DLPD3V3LC Document number: DS30662 Rev. 9 - 3 1 of 4 www.diodes.com November 2009 © Diodes Incorporated DLPD3V3LC NOT RECOMMENDED FOR NEW DESIGNS 3.3V LOW CAPACITANCE BIDIRECTIONAL TVS Features • 330 Watts Peak Pulse Power (tp = 8x20 μs) • Transient Protection for data, signal, and VCC bus to IEC61000-4-2 level 4 (ESD) • Low Capacitance, typ. <3 pF • Bidirectional Configuration • Surface Mount Package Ideally Suited for Automated Insertion • Lead Free By Design/RoHS Compliant (Note 3) • "Green" Device (Note 4) Mechanical Data • Case: SOT-26 • Case Material: Molded Plastic, “Green” Molding Compound, Note 4. UL Flammability Classification Rating 94V-0 • Moisture Sensitivity: Level 1 per J-STD-020 • Terminal Connections: See Diagram • Terminals: Finish - Matte Tin annealed over Copper leadframe. Solderable per MIL-STD-202, Method 208 • Marking Information: See Page 2 • Ordering Information: See Page 2 • Weight: 0.017 grams (approximate) Maximum Ratings, Total Device @TA = 25°C unless otherwise specified Characteristic Symbol Value Unit Peak Pulse Power (Note 2) Ppk 330 W Thermal Characteristics Characteristic Symbol Value Unit Thermal Resistance, Junction to Ambient (Note 5) RθJA 286 °C/W Operating and Storage Temperature Range TJ, TSTG -55 to +150 °C Electrical Characteristics @TA = 25°C unless otherwise specified Reverse Standoff Voltage Breakdown Voltage VBR @ IT Test Current Max. Reverse Leakage @ VRWM (Note 7) Max. Clamping Voltage @ Ip = 1A (Note 2) Max. Clamping Voltage VC @ IPP (Note 2) Max. Peak Pulse Current (Note 2) Typical Total Capacitance (Note 1) VRWM (V) Min (V) Max (V) IT (mA) IR (mA) VC (V) (V) IPP (A) (pF) 3.3 4.0 ⎯ 1.0 0.11 8.0 22 15 2.5 Notes: 1. VR = 0V, f = 1MHz as measured between pins 1 and 3. 2 . tp = 8x20 μs. See figure 2. 3. No purposefully added lead. 4. Diodes Inc.'s "Green" policy can be found on our website at http://www.diodes.com/products/lead_free/index.php. 5. Device mounted on FR-4 PCB with pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. 6. From pin 3 to pin 1, and/or from pin 1 to pin 3. 7. Short duration pulse test used to minimize self-heating effect. Top View Device Schematic and Pin Out Configuration Please click here to visit our online spice models database. |
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Similar Description - DLPD3V3LC |
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