SC9RS08KA2 datasheet(57/134 Pages) FREESCALE

57 / 134 page

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

Chapter 8

Central Processor Unit (RS08CPUV1)

8.1

Introduction

This chapter is a summary of information about the registers, addressing modes, and instruction set of the

RS08 Family CPU. For a more detailed discussion, refer to the RS08 Core Reference Manual, volume 1,

Freescale Semiconductor document order number RS08RMv1.

The RS08 CPU has been developed to target extremely low-cost embedded applications using a

process-independent design methodology, allowing it to keep pace with rapid developments in silicon

processing technology.

The main features of the RS08 core are:

•

Streamlined programmer’s model

•

Subset of HCS08 instruction set with minor instruction extensions

•

Minimal instruction set for cost-sensitive embedded applications

•

New instructions for shadow program counter manipulation, SHA and SLA

•

New short and tiny addressing modes for code size optimization

•

16K bytes accessible memory space

•

Reset will fetch the first instruction from $3FFD

•

Low-power modes supported through the execution of the STOP and WAIT instructions

•

Debug and FLASH programming support using the background debug controller module

•

Illegal address and opcode detection with reset

8.2

Programmer’s Model and CPU Registers

Figure 8-1 shows the programmer’s model for the RS08 CPU. These registers are not located in the

memory map of the microcontroller. They are built directly inside the CPU logic.

SC9RS08KA2 Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc