LTC2472CDDPBF datasheet(9/20 Pages) LINER

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LTC2470/LTC2472

24702f

before the conclusion of the POR cycle. The POR signal

clears all internal registers. Following the POR signal, the

LTC2470/LTC2472 start a conversion cycle and follow the

succession of states shown in Figure 2. The reference

startup time following a POR is 12ms (CCOMP = CREFOUT =

0.1μF). The ﬁrst conversion following power-up will be

invalid since the reference voltage has not completely

settled. The ﬁrst conversion following power up can be

discarded using the data abort command or simply read

and ignored. Depending on the value chosen for CCOMP

and CREFOUT, the reference startup can take more than one

conversion period, see Figure 3. If the startup time is less

than 1ms (1ksps output rate) or 4ms (250sps output rate)

then conversions following the ﬁrst period are accurate

to the device speciﬁcations. If the startup time exceeds

1ms or 4ms then the user can wait the appropriate time

or use the ﬁxed conversion period as a startup timer by

ignoring results within the unsettled period. Once the

reference has settled, all subsequent conversion results

are valid. If the user places the device into the sleep mode

(SLP = 1, reference powered down) the reference will

require a startup time proportional to the value of CCOMP

and CREFOUT (see Figure 3).

Ease of Use

The LTC2470/LTC2472 data output has no latency, ﬁlter

settling delay, or redundant results associated with the

conversion cycle. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog input voltages requires no

special actions.

The LTC2470/LTC2472 include a proprietary input sampling

scheme that reduces the average input current by several

orders of magnitude when compared to traditional delta-

sigma architectures. This allows external ﬁlter networks

to interface directly to the LTC2470/LTC2472. Since the

average input sampling current is 50nA, an external RC

lowpass ﬁlter using 1kΩ and 0.1μF results in <1LSB

additional error. Additionally, there is negligible leakage

current between IN+ and IN– (for the LTC2472).

Input Voltage Range (LTC2470)

Ignoring offset and full-scale errors, the LTC2470 will

theoretically output an “all zero” digital result when the

input is at ground (a zero scale input) and an “all one”

digital result when the input is at VREF or higher (VREFOUT

= 1.25V). In an underrange condition (for all input voltages

below zero scale) the converter will generate the output

code 0. In an overrange condition (for all input voltages

greater than VREF) the converter will generate the output

code 65535.

Input Voltage Range (LTC2472)

As detailed in the Output Data Format section, the output

code is given as 32768 • (VIN+ – VIN–)/VREF + 32768. For

(VIN+ – VIN–) ≥ VREF, the output code is clamped at 65535

(all ones). For (VIN+ – VIN–) ≤ –VREF, the output code is

clamped at 0 (all zeroes).

Output Data Format

The LTC2470/LTC2472 generates a 16-bit direct binary

encoded result. It is provided as a 16-bit serial stream

through the SDO output pin under the control of the SCK

input pin (see Figure 5).

The LTC2472 (differential input) output code is given by

32768 • (VIN+ – VIN–)/VREF + 32768. The ﬁrst bit output

by the LTC2472, D15, is the MSB, which is 1 for VIN+ ≥

VIN– and 0 for VIN+ < VIN–. This bit is followed by succes-

sively less signiﬁcant bits (D14, D13, …) until the LSB is

output by the LTC2472, see Table 1.

The LTC2470 (single-ended input) output code is a direct

binary encoded result, see Table 1.

During the data output operation the CS input pin must

be pulled low (CS = LOW). The data output process starts

with the most signiﬁcant bit of the result being present at

the SDO output pin (SDO = D15) once CS goes low. A new

data bit appears at the SDO output pin after each falling

edge detected at the SCK input pin. The output data can

be reliably latched on the rising edge of SCK.

APPLICATIONS INFORMATION

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