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MAS6501BA1ST206 Datasheet(PDF) 6 Page - Micro Analog systems |
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MAS6501BA1ST206 Datasheet(HTML) 6 Page - Micro Analog systems |
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6 / 16 page ![]() DA6501.001 27 October 2008 6 (16) I 2C SERIAL INTERFACE CONTROL Serial Interface MAS6501 has two wire serial I2C bus type interface comprising of serial clock (SCL) and serial data (SDA) pins. I2C bus is used to write configuration data to sensor interface IC and read the measurement result when A/D conversion has been finished. Digital interface includes also master clock (MCLK), end of conversion (EOC) and master reset (XCLR) pins. MLCK signal is needed to be clocked during conversion period. It can be stopped after EOC goes high which indicates that A/D conversion has been accomplished. MCLK signal can also be running all the time. XCLR is used to reset the A/D converter. Reset initializes internal registers and counters. After connecting supply voltage to MAS6501 and before starting operating the device via I2C bus it is required to reset the device with XCLR reset pin if supply voltage rise time has been longer than 400 ns. If the supply voltage rise time is shorter than this the external reset with XCLR pin is unnecessary since the device is automatically reset by power on reset (POR) circuitry. Device and Register Addresses I2C bus standard makes it possible to connect several I2C bus devices into same bus. The devices are distinguished from each other by unique device address codes. MAS6501 device address is shown in table 2. The LSB bit of the device address defines whether the bus is configured to Read (1) or Write (0) operation. Table 2. MAS6501 device address A7 A6 A5 A4 A3 A2 A1 W/R 1 1 1 0 1 1 1 0/1 MAS6501 contains three 8-bit registers which are presented in table 3. Control register is used to configure the device to proper measurement setup. Control register bits are described in table 1 (page 5). Two other 8-bit registers are used to store the 16-bit A/D conversion result. Table 3. MAS6501 internal register addresses A7 A6 A5 A4 A3 A2 A1 A0 Register Description 1 1 1 1 1 1 0 1 MSB A/D Conversion Result Register 1 1 1 1 1 1 1 0 LSB A/D Conversion Result Register 1 1 1 1 1 1 1 1 Control register |
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