AT91SAM9260 datasheet(21/47 Pages) ATMEL

21 / 47 page

6221JS–ATARM–17-Jul-09

AT91SAM9260

A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the

Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional

features.

Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks 1 to

7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to

EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level

of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals

and provides access to the Advanced Peripheral Bus (APB).

Other areas are unused and performing an access within them provides an abort to the master

requesting such an access.

Each Master has its own bus and its own decoder, thus allowing a different memory mapping

per Master. However, in order to simplify the mappings, all the masters have a similar address

decoding.

Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are

assigned to the memory space decoded at address 0x0: one for internal boot, one for external

boot, one after remap. Refer to Table 8-1, “Internal Memory Mapping,” on page 21 for details.

A complete memory map is presented in Figure 8-1 on page 20.

8.1

Embedded Memories

• 32 KB ROM

– Single Cycle Access at full matrix speed

• Two 4 KB Fast SRAM

– Single Cycle Access at full matrix speed

8.1.1

Boot Strategies

Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap

status and the BMS state at reset.

The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,

the memory layout can be configured with two parameters.

REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This

is done by software once the system has booted. Refer to the Bus Matrix Section for more

details.

When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an

external memory. This is done via hardware at reset.

Note:

Memory blocks not affected by these parameters can always be seen at their specified base

addresses. See the complete memory map presented in

Figure 8-1 on page 20.

Table 8-1.

Internal Memory Mapping

Address

REMAP = 0

REMAP = 1

BMS = 1

BMS = 0

0x0000 0000

ROM

EBI_NCS0

SRAM0 4K

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