EM68932DVKB datasheet(3/40 Pages) ETRON

3 / 40 page

EtronTech

EM68932DVKB

Etron Confidential

Rev. 1.0

Aug. 2009

Pin Descriptions

Table 2. Pin Details of EM68932D

Symbol

Type

Description

CK, CK

Input

Differential Clock: CK and CK are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive edge of CK and

negative edge of CK . Input and output data is referenced to the crossing of CK and

CK (both directions of the crossing)

CKE

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.

Internal clock signals and device input buffers and output drivers. Taking CKE Low

provides Precharge Power Down and Self Refresh operation (all banks idle) or

Active Power Down (Row Active in any bank). CKE is synchronous for all functions

except for disabling outputs, which is asynchronous. Input buffers, excluding

CK, CK and CKE, are disabled during Power Down and Self Refresh modes to

reduce standby power consumption.

BA0, BA1

Input

Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write,

or BankPrecharge command is being applied. BA0 and BA1 also determine which

mode register (MRS or EMRS) is loaded during a Mode Register Set command.

A0-A11

Input

Address Inputs: A0-A11 are sampled during the BankActivate command (row

address A0-A11) and Read/Write command (column address A0-A7 with A10

defining Auto Precharge).

Input

Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the

command decoder. All commands are masked when CS is sampled HIGH.

CS provides for external bank selection on systems with multiple banks. It is

considered part of the command code.

RAS

Input

Row Address Strobe: The RAS signal defines the operation commands in

conjunction with the CAS and WE signals and is latched at the positive edges of

CK. When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either

the BankActivate command or the Precharge command is selected by the WE

signal. When the WE is asserted "HIGH," the BankActivate command is selected

and the bank designated by BA is turned on to the active state. When the WE is

asserted "LOW," the Precharge command is selected and the bank designated by

BA is switched to the idle state after the precharge operation.

CAS

Input

Column Address Strobe: The CAS signal defines the operation commands in

conjunction with the RAS and WE signals and is latched at the positive edges of

CK. When RAS is held "HIGH" and CS is asserted "LOW," the column access is

started by asserting CAS "LOW." Then, the Read or Write command is selected

by asserting WE "HIGH " or LOW"."

Input

Write Enable: The WE signal defines the operation commands in conjunction

with the RAS and CAS signals and is latched at the positive edges of CK. The

WE input is used to select the BankActivate or Precharge command and Read or

Write command.

DQS0 -DQS3

Input /

Output

Bidirectional Data Strobe: The DQSx signals are mapped to the following data

bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, and DQS3

to DQ24-DQ31.

DM0 - DM3

Input

Data Input Mask: DM0-DM3 are byte specific. Input data is masked when DM is

sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23-

DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0.

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