AT90SCR100 datasheet(250/433 Pages) ATMEL

250 / 433 page

250

TPR0327AY–SMS–30Jan09

AT90SCR100

The UDRE0 flag indicates if the transmit buffer (UDR0) is ready to receive new data. If UDRE0 is

one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag can generate a

Data Register Empty interrupt (see description of the UDRIE0 bit).

UDRE0 is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FE0: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.,

when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the

receive buffer (UDR0) is read. The FE0 bit is zero when the stop bit of received data is one.

Always set this bit to zero when writing to UCSR0A.

• Bit 3 – DOR0: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive

buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a

new start bit is detected. This bit is valid until the receive buffer (UDR0) is read. Always set this

bit to zero when writing to UCSR0A.

• Bit 2 – UPE0: USART Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received and the

Parity Checking was enabled at that point (UPM01 = 1). This bit is valid until the receive buffer

(UDR0) is read. Always set this bit to zero when writing to UCSR0A.

• Bit 1 – U2X0: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-

chronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-

bling the transfer rate for asynchronous communication.

• Bit 0 – MPCM0: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCM0 bit is written to

one, all the incoming frames received by the USART Receiver that do not contain address infor-

mation will be ignored. The Transmitter is unaffected by the MPCM0 setting. For more detailed

information see “Multi-processor Communication Mode” on page 247.

18.11.3

UCSR0B – USART Control and Status Register B

• Bit 7 – RXCIE0: RX Complete Interrupt Enable 0

Writing this bit to one enables interrupt on the RXC0 Flag. A USART Receive Complete interrupt

will be generated only if the RXCIE0 bit is written to one, the Global Interrupt Flag in SREG is

written to one and the RXC0 bit in UCSR0A is set.

• Bit 6 – TXCIE0: TX Complete Interrupt Enable 0

Bit

7654

$0000C1

RXCIE0

TXCIE0

UDRIE0

RXEN0

TXEN0

UCSZ02

RXB80

TXB80

UCSR0B

Read/write

R/W

Initial value

0000

0x00

AT90SCR100 Datasheet(PDF) 250 Page - ATMEL Corporation

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