AT90SCR100 datasheet(324/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

• Two or more masters are performing identical communication with the same Slave. In this

case, neither the Slave nor any of the masters will know about the bus contention.

• Two or more masters are accessing the same Slave with different data or direction bit. In this

case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters

trying to output a one on SDA while another Master outputs a zero will lose the arbitration.

Losing masters will switch to not addressed Slave mode or wait until the bus is free and

transmit a new START condition, depending on application software action.

• Two or more masters are accessing different slaves. In this case, arbitration will occur in the

SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose

the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are

being addressed by the winning Master. If addressed, they will switch to SR or ST mode,

depending on the value of the READ/WRITE bit. If they are not being addressed, they will

switch to not addressed Slave mode or wait until the bus is free and transmit a new START

condition, depending on application software action.

This is summarized in Figure 22-21. Possible status values are given in circles.

Figure 22-21.

Possible Status Codes Caused by Arbitration

22.9

TWI Register Description

22.9.1

TWBR – TWI Bit Rate Register

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency

divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator

Unit” on page 303 for calculating bit rates.

Own

Address / General Call

received

Arbitration lost in SLA

TWI bus will be released and not addressed slave mode will be entered

A START condition will be transmitted when the bus becomes free

Arbitration lost in Data

Direction

Yes

Write

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be returned

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

Read

68/78

SLA

START

Data

STOP

Bit

7654

$0000B8

TWBR7

TWBR6

TWBR5

TWBR4

TWBR3

TWBR2

TWBR1

TWBR0

TWBR

Read/write

R/W

Initial value

0000

0x00

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