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AT90SCR100 Datasheet(PDF) 328 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 328 Page - ATMEL Corporation |
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328 / 433 page  328 TPR0327AY–SMS–30Jan09 AT90SCR100 22.9.6 TWAMR – TWI (Slave) Address Mask Register • Bits 7..1 – TWAM: TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. Figure 22-22 shows the address match logic in detail. Figure 22-22. TWI Address Match Logic, Block Diagram • Bit 0 – Res: Reserved Bit This bit is reserved and will always read as zero. Bit 7654 3 2 1 0 $0000BD TWAM [6:0] - TWAMR Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0000 0 0 0 0 0x00 Address Match Address Bit Comparator 0 Address Bit Comparator 6..1 TWAR0 TWAMR0 Address Bit 0 |
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