AT90SCR100 datasheet(387/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

29.8.2

AVR_RESET (0xC)

The AVR specific public JTAG instruction to set the AVR device in the Reset mode or to take the

device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit

Reset Register is selected as Data Register. Note that the reset will be active as long as there is

a logic “one” in the Reset Chain. The output from this chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

29.8.3

PROG_ENABLE (0x4)

The AVR specific public JTAG instruction to enable the programming via the JTAG port. The 16-

bit Programming Enable Register is selected as Data Register. The active states are the

following:

• Shift-DR: The programming enable signature is shifted into the Data Register.

• Update-DR: The programming enable signature is compared to the correct value, and

Programming mode is entered if the signature is valid.

29.8.4

PROG_COMMANDS (0x5)

The AVR specific public JTAG instruction for entering programming commands via the JTAG

port. The 15-bit Programming Command Register is selected as Data Register. The active

states are the following:

• Capture-DR: The result of the previous command is loaded into the Data Register.

• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous

command and shifting in the new command.

• Update-DR: The programming command is applied to the Flash inputs

• Run-Test/Idle: One clock cycle is generated, executing the applied command

29.8.5

PROG_PAGELOAD (0x6)

The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.

An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs

of the Programming Command Register. The active states are the following:

• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.

• Update-DR: The content of the Flash Data Byte Register is copied into a temporary register.

A write sequence is initiated that within 11 TCK cycles loads the content of the temporary

and the high byte for each new Update-DR state, starting with the low byte for the first

Update-DR encountered after entering the PROG_PAGELOAD command. The Program

Counter is pre-incremented before writing the low byte, except for the first written byte. This

ensures that the first data is written to the address set up by PROG_COMMANDS, and

loading the last location in the page buffer does not make the program counter increment into

the next page.

29.8.6

PROG_PAGEREAD (0x7)

The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port.

An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs

of the Programming Command Register. The active states are the following:

AT90SCR100 Datasheet(PDF) 387 Page - ATMEL Corporation

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