AT32AP7000 datasheet(21/973 Pages) ATMEL

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32003M–AVR32–09/09

AT32AP7000

6.2.5

Caches and write buffer

AVR32 AP implements 16K data and 16K instruction caches. The caches are 4-way set asso-

ciative. Each cache has a 32-bit System Bus master interface connecting it to the bus. The

instruction cache has a 32-bit interface to the fetch pipeline stage, and the data cache has a 64-

bit interface to the load-store pipeline. The caches use a least recently used allocate-on-read-

miss replacement policy. The caches are virtually tagged, physically indexed, avoiding the need

to flush them on task switch.

The caches provide locking on a per-line basis, allowing code and data to be permanently

locked in the caches for timing-critical code. The data cache also allows prefetching of data

using the pref instruction.

Accesses to the instruction and data caches are tagged as cacheable or uncacheable on a per-

page basis by the MMU. Data cache writes are tagged as write-through or writeback on a per-

page basis by the MMU.

The data cache has a 32-byte combining write buffer, to avoid stalling the CPU when writing to

external memory. Writes are tagged as bufferable or unbufferable on a per-page basis by the

MMU. Bufferable writes to sequential addresses are placed in the buffer, allowing for example a

sequence of byte writes from the CPU to be combined into word transfers on the bus. A sync

instruction is provided to explicitly flush the write buffer.

6.2.6

Unaligned reference handling

AVR32 AP has hardware support for performing unaligned memory accesses. This will reduce

the memory footprint needed by some applications, as well as speed up other applications oper-

ating on unaligned data.

AVR32 AP is able to perform certain word-sized load and store instructions of any alignment,

and word-aligned st.d and ld.d. Any other unaligned memory access will cause an MMU address

exception. All coprocessor memory access instructions require word-aligned pointers. Double-

word-sized accesses with word-aligned pointers will automatically be performed as two word-

sized accesses.

The following table shows the instructions with support for unaligned addresses. All other

instructions require aligned addresses. Accessing an unaligned address may require several

clock cycles, refer to the AVR32 AP Technical Reference Manual for details.

Table 6-1.

Instructions with unaligned reference support

Instruction

Supported alignment

ld.w

Any

st.w

Any

lddsp

Any

lddpc

Any

stdsp

Any

ld.d

Word

st.d

Word

All coprocessor memory access instruction

Word

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