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HM62V8100I Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # HM62V8100I
Description  Wide Temperature Range Version 8 M SRAM (1024-kword 8-bit)
PDF  16 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HM62V8100I Datasheet(HTML) 9 Page - Renesas Technology Corp

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HM62V8100-I Series
Write Cycle
HM62V8100I
-5
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
tWC
55
—
ns
Address valid to end of write
tAW
50
—
ns
Chip selection to end of write
tCW
50
—
ns
5
Write pulse width
tWP
40
—
ns
4
Address setup time
tAS
0
—
ns
6
Write recovery time
tWR
0
—
ns
7
Data to write time overlap
tDW
25
—
ns
Data hold from write time
tDH
0
—
ns
Output active from end of write
tOW
5
—
ns
2
Output disable to output in High-Z
tOHZ
0
20
ns
1, 2
Write to output in high-Z
tWHZ
0
20
ns
1, 2
Notes: 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from
device to device.
4. A write occures during the overlap of a low
CS1, a high CS2, a low WE. A write begins at the latest transition
among
CS1 going low, CS2 going high, WE going low. A write ends at the earliest transition among CS1
going high, CS2 going low,
WE going high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle.
Rev.2.00, Nov.02.2009, page 9 of
15



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