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M16C65 Datasheet(PDF) 73 Page - Renesas Technology Corp |
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M16C65 Datasheet(HTML) 73 Page - Renesas Technology Corp |
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73 / 112 page  REJ03B0257-0110 Rev.1.10 Sep 24, 2009 Page 73 of 109 M16C/65 Group 5. Electrical Characteristics Figure 5.12 Timing Diagram Memory Expansion Mode and Microprocessor Mode (Effective in wait state setting) BCLK HOLD input HLDA input P0, P1, P2, P3, P4, P5_0 to P5_2 (1) (Common to wait state and no wait state settings) Note: 1. These pins are high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register, and PM11 bit in PM1 register. Hi−Z RDY input RD BCLK (Separate bus) (Multiplexed bus) WR, WRL, WRH RD (Separate bus) WR, WRL, WRH (Multiplexed bus) tsu(RDY-BCLK) th(BCLK-RDY) tsu(HOLD-BCLK) th(BCLK-HOLD) td(BCLK-HLDA) td(BCLK-HLDA) Measuring conditions V = V = 5 V CC1 CC2 Input timing voltage: V = 1.0 V, V = 4.0 V IL IH Output timing voltage: V = 2.5 V, V = 2.5 V OL OH V = V = 5 V CC1 CC2 |
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